JEDEC and the JC-42.6 Subcommittee for Low Power Memories has announced the publication of the new JESD209-5B standard which now includes improvements to LPDDR5, as well as an extension for the standard in the form of new LPDDR5X.
The new LPDDR5X standard is an evolutionary step over LPDDR5, further increasing the data rates possible by 33% from 6400Mbps to 8533Mbps.
The industry had first shifted over to the LPDDR5 memory standard back in 2020, with the first generation SoCs and memory modules running at a speed of 5500Mbps which had gotten an upgrade to 6400Mbps speeds in recent 2021 flagship devices.
As IP vendors and DRAM manufacturers have matured their LPDDR5 products, there’s an increasing need to look for further updates to the LPDDR5 standard as we’ve essentially reached the maximum data rates of the standard in current generation implementations.
| LPDDR Generations | ||||
| LPDDR3 | LPDDR4 | LPDDR4X | LPDDR5 | LPDDR5X |
| Max Density | 32 Gbit | 64 Gbit | 32 Gbit | |
| Max Data Rate | 2133Mbps | 4266Mbps | 6400Mbps | 8533Mbps |
| Channels | 1 | 2 | 1 | |
| Width | x32 | x32 (2x x16) | x16 | |
| Banks (Per Channel) |
8 | 8 | 8-16 | 16 |
| Bank Grouping | No | No | Yes | |
| Prefetch | 8n | 16n | 16n | |
| Voltage | 1.2v | 1.1v | Variable (Max 1.1v) |
|
| Vddq | 1.2v | 1.1v | 0.6v | 0.6v |
While we currently don’t have access to the official documentation to detail the exact changes, back in February Cadence had written more extensively about the new improvements in LP5X over LP5:
- To Improve READ SI performance in the dual rank system at high speeds that Lpddr5X devices support a Unified NT-ODT Behavior has been defined. Unified NT-ODT is a requirement for all LPDDR5X devices
- To support high data rates for Lpddr5X, we need a way to compensate for transmission loss. This has been achieved by defining the pre-emphasis function. Lpddr5X devices have pull up or down pre-emphasis for each of the lower/upper byte lane programming.
- Rx Offset Calibration Training – LPDDR5X SDRAM provides Offset Calibration Training for adjusting DQ Rx offset and Offset Calibration Training is recommended for every power-up and initialization training sequence to cope with the SDRAM operating condition change
- Extended Latencies – LPDDR5X SDRAM devices support extended Read, Write, nWR, ODTLon and ODTLoff Latency Values to account for longer number of cycle it takes to do the data access to memory array. WCK2CK Sync AC Parameters are also extended.
- LPDDR5X SDRAM Devices support Per-pin controlled Decision Feedback Equalization: DFE. This includes new Mode Registers 70/71/72/73/74.
- New LPDDR5X SDRAM Device specific Clock AC Timings for 937.5/1066.5MHz and Write Clock AC Timings for 3750/4266.5MHz.
- New Mode register fields or additional conditions on the use of existing fields have been added to several Mode registers for LPDDR5X devices. Some of the examples of changed MR are MR0, MR1, MR2, MR13, MR15, MR41, MR58, MR69, etc.
- LPDDR5X SDRAM devices do not support 8 Bank Mode of operations. 8 Bank Mode doesn’t offer the architectural benefit of more bank interleaving resources and core operation timings at high speed that 16B and BG Mode have. It is specially limiting for high speed LPDDR5X devices support leading JEDEC to drop 8 Bank Mode support for LPDDR5X.
In short, the new standard covers deeper tweaks to the architecture and operating mode of the memory standard to achieve higher data-rates.
For eventual mobile SoCs using 8533Mbps memory, the peak theoretical available bandwidth would grow from 51.2GB/s to 68.26GB/s, allowing future designs to further increase CPU and GPU performances. It’s to be noted, that we haven’t heard much about power efficiency improvements of the new LP5X standard, so I assume that we’ll be relying on DRAM vendors to improve power efficiency via more advanced manufacturing nodes to keep total power usage inside of devices in check.
I estimate we’ll be seeing LPDDR5X in future late 2022 or 2023 SoCs.
